Method for modeling varactor by direct extraction of parameters

ABSTRACT

A method for modeling a varactor with a MOS structure, and transforms an s-parameter obtained by the measurement using measurement equipment into a y-parameter and a z-parameter and then directly extracts parameters required for the modeling by means of equations in accordance with embodiments. The modeling can be made reflecting the parameters of the varactor varied according to frequency so that the more accurate RF modeling of a passive device can be made and the accurate modeling of the varactor can be made through the direct extraction method of the parameters so that the parameters of the varactor having a physical meaning can be extracted without using an expensive CAD tool, the time required for optimizing the parameters can be reduced, a computing time can be shorten, an initial condition dependence generated in performing the optimization is not required, and a pattern for a test is not required.

The present application claims priority under 35 U.S.C. 119 to KoreanPatent Application No. 10-2006-0137299 (filed on Dec. 29, 2006), whichis hereby incorporated by reference in its entirety.

BACKGROUND

The process of manufacturing a semiconductor integrated circuit (IC)device may be very complicated and expensive. Therefore, prior toactually manufacturing the IC device, the IC device may be subjected toa simulation process verifying that it is operated according to aspecified design. The most representative program used for an operationsimulation of a circuit is a simulation program with integrated circuitemphasis (SPICE). The SPICE simulates a circuit model by using equationsmathematically defining the operation of several circuit devicesincluded in the circuit design and then provides the results asverification information. In order to simulate the circuit, variousdevices should be modeled. For this, a Berkeley short-channel (BSIM)insulated-gate field effect transistor (IGFET) has been the most widelyused.

A varactor may be implemented having a MOS structure in a semiconductorintegrated circuit device. Such a MOS varactor may have a high Q indexand may occupy a small area when compared to a pn junction-typevaractor. The MOS varactor may be used as an LC tank of a voltagecontrolled oscillator (VCO) for generating different VCO oscillatingfrequencies. The MOS varactor is one of important RF passive devicessuch as an analog filter, a switch capacitor circuit, a data converter,an RF circuit, and the like that may be applied to various fields. Sincethe characteristics of the MOS varactor may be varied according to theoperating frequency, a physical geometry of the device, and a biascondition, an RF modeling is important.

However, in the modeling of the varactor, since the real component ofimpedance may be determined by the serial connection of R, L, and C, itmay have a value that is not varied according to frequency. However, thereal component in the actual measured value of impedance may varyaccording to frequency. The existing modeling method cannot explain thischange. Accordingly, since it may be difficult to accurately model thedevice, the operation prediction of the circuit may not be accurate.

Moreover, optimally modeling the varactor using a CAD tool may betime-consuming and incurs a great deal of expense.

SUMMARY

Embodiments relate to a method for modeling a varactor, and moreparticularly to an RF modeling method of a varactor through a directextraction method of parameters for explaining the parameters of thevaractor varied according to frequency. Embodiments relate to anaccurate RF modeling method of a varactor. Embodiments relate to an RFmodeling method capable of explaining the change of parameters in avaractor according frequency. Embodiments relate to reducing the timerequired to extract parameters of a varactor having a physical meaningand optimize the parameter without using an expensive CAD tool.

DRAWINGS

Example FIG. 1 illustrates a varactor, in accordance with embodiments.

Example FIG. 2 illustrates an equivalent circuit diagram of a varactor,in accordance with embodiments.

Example FIG. 3A illustrates a real component Re(Z_(A)) of port 1 gateimpedance Z_(A) obtained through a parameter direction extractionmethod, in accordance with embodiments.

Example FIG. 3B illustrates an imaginary component Im(Z_(A)) of port 1gate impedance Z_(A) obtained through a parameter direction extraction,in accordance with embodiments.

Example FIG. 4A illustrates −1/Im(Z_(A)) of port 1 gate impedance Z_(A)obtained through a parameter direction extraction method, in accordancewith embodiments.

Example FIG. 4B illustrates −1/Im(Z_(A))/ω of port 1 gate impedanceZ_(A) obtained through a parameter direction extraction method, inaccordance with embodiments.

Example FIGS. 5A and 5B illustrates the parameters in question forobtaining L_(gate) through a parameter direction extraction method inaccordance with embodiments.

Example FIGS. 6A to 6G illustrate an s-parameter plot from a comparisonof an s-parameter obtained through a parameter direction extractionmethod in accordance with embodiments and an s-parameter obtainedthrough a measurement using measurement equipment.

DESCRIPTION

As illustrated in example FIGS. 1 and 2, MOS varactor 10 can be formedof a structure (i.e., a branch) including a pair of MOS capacitors 20formed on and/or over a semiconductor substrate such as p-typesemiconductor substrate 12. Each MOS capacitor can include gateinsulating film 22 formed on and/or over semiconductor substrate 12 andgate electrode 24 formed on and/or over gate insulating film 22. A pairof spacers 25 can be formed on sidewalls of gate insulating film 22 andgate electrode 24. Source 26 and drain 28 can be formed under sidewalls25 in an n+ area of semiconductor substrate 12.

P-type substrate 12 can be connected to a ground through p+ region 14.Gate electrode 24 may be connected to common gate electrode (Gate) whichis Port 1. Source 26 and drain 28 can be electrically connected to bulkterminal (Bulk). The bulk terminal in MOS varactor 10 having a 2-portnetwork structure can be connected to ground through the P-typesubstrate 12.

As illustrated in example FIG. 2, in an equivalent circuit diagram,L_(gate) can serve as an overall inductance of Port 1 via and a gate.R_(gate) can serve as a unit cell via/contact resistance of Port 1 andthe gate. C_(par) can serve as a parasitic capacitance of the varactorwhile C_(gate) can serve as a variable capacity of a MOS-type variablecapacitance. R_(sd) can serve as a unit cell via/contact resistance ofPort 2 and a bulk. L_(sd) can serve as an overall inductance of Port 2via and the bulk terminal. D_(nwpsub) can serve as a diode providedbetween an N-well and P-type substrate 12. R_(sub) can serve as aresistor for P-type substrate 12 and C_(sub) can serve as a capacitor ofP-type substrate 12.

C_(gate) can be represented by equation 1 below, wherein C_(gmin) iscapacitance in the largest reverse bias, dC_(g) is capacity coefficient,V_(g) is potential difference across C_(gate), and dV_(g) and V_(gnorm)are voltage coefficient.C _(gate) =C _(gmin) +dC _(g)×[1+tan h[(V _(g) −dV _(g))/V_(gnorm)]]  (1)

In accordance with embodiments, the following fact and devises can beprovided in a method for modeling the varactor using a direct extractionmethod based on the fact.

First, unlike an inductor that requires the accurate modeling of thesubstrate in order to make Q index large since the loss due to thesubstrate is large, the varactor in accordance with embodiments has asufficiently large Q index and the influence of the characteristics ofthe substrate on the characteristics of the varactor is relativelysmall.

Secondly, for the varactor in accordance with embodiments, Rgate canserve as a resistance component by way of a polysilicon regardless of agate bias. Third, L_(gate) can have an inductance value through the gateconnection. Fourth, C_(ox) can serve as a capacitor by way of a gateinsulating film (oxide film). Fifth, C_(gate) can serve as a capacitormade by way of a depletion layer, whereby its value can be very small ina depletion state. However, when the accumulation state by the increaseof voltage, its value can be large. Sixth, R_(sd) can be represented bychannel resistance from the source to the depletion layer. Lastly, thereal component of Port 1 gate impedance Z_(A) and Port 2 bulk impedanceZ_(B) can be high in frequency dependence.

In order to obtain Port 1 impedance Z_(A), Port 2 impedance Z_(B) andsubstrate impedance Z_(C) in the measured s-parameter, when transformingthe measured s-parameter into a y-parameter and a z-parameter and thenusing the following equations 2 to 8 devised in accordance withembodiments, the values of R_(gate), C_(var), L_(gate), R_(sd), andL_(sd) can be directly extracted without separately using an expensiveCAD tool. Herein, the parameter C_(var) can be formed of Cgate and Cparas illustrated in example FIG. 2. Parasitic capacitance Cpar of thevaractor can be associated with gate leakage current, whereby if thisvalue is small enough to be disregarded, Cvar and Cgate can be the same.

$\begin{matrix}{{{Re}\left( Z_{A} \right)} = {{{Re}\left( {Z_{11} - Z_{12}} \right)} = R_{gate}}} & (2) \\{{{Im}\left( Z_{A} \right)} = {{{Im}\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}} & (3) \\{\frac{1}{{Im}\left( Z_{A} \right)} = {\frac{1}{{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}} = {\frac{{- \omega}\; C_{var}}{1 - {\omega^{2}L_{gate}C_{var}}} \approx {{- \omega}\; C_{var}}}}} & (4) \\{{{Im}\left( Z_{A} \right)} = {{{Im}\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}} & (5) \\{{{Im}\left( Z_{A} \right)} + {\frac{1}{\omega\; C_{var}}\omega\; L}} & (6) \\{{{Re}\left( Z_{B} \right)} = {{{Re}\left( {Z_{22} - Z_{12}} \right)} = R_{sd}}} & (7) \\{{{Im}\left( Z_{B} \right)} = {{{Im}\left( {Z_{22} - Z_{12}} \right)} = {j\;\omega\; L_{sd}}}} & (8)\end{matrix}$

In the above equations 2 to 8, Z₁₁, Z₁₂, Z₂₁, and Z₂₂ can be valuesobtained by transforming the s-parameter obtained by measurementequipment such as a vector network analyzer, where ω can be a constantand C_(j) can be junction capacitance between the n+ area and the p-typesubstrate.

The R_(gate) of parameters directly extracted using the above equations2 to 8 is illustrated in example FIGS. 3A and 3B, the C_(var) isillustrated in example FIGS. 4A and 4B, and L_(gate) is illustrated inFIGS. 5A and 5B.

The real component and imaginary component of substrate impedance Zc canbe represented by the following equations:

$\begin{matrix}{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = \frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}}} & (9) \\{\frac{- 1}{{Im}\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}} & (10)\end{matrix}$

In a low frequency area of equation 10, R_(sub) can be obtained andthus, C_(sub) can be obtained using equation 11.

The varactor illustrated in example FIG. 1 can be manufactured using a0.13 μm CMOS process, whereby the varactor can be structured in a combstructure in order to reduce serial parasitic resistance. In themanufactured varactor in accordance with embodiments, a line width ofmetal can be 2.5 μm, its length can be 2 μm, a branch can be 1, andN_(f) can be 32. In such a varactor and which is in a wafer state, thes-parameter can be measured from 100 MHz to 10.1 GHz using an E8361Avector network analyzer and a cascade RF probe. Since the parasiticcomponent is included in the wafer state, a two-step de-embedding can beperformed to correct this.

As illustrated in example FIGS. 6A to 6G, the comparison result of thes-parameter measured on the varactor manufactured in accordance withembodiments and the parameters directly extracted through equations 2 to11. Parameters S(4,4), S(4,3), S(3,3), S(3,1) are parameters directlyextracted through the equations provided in accordance with embodimentsand parameters S(2,2), S(2,1), S(1,2), S(1,1) are values measured by wayof the equipment under the conditions described above.

As illustrated in the s-parameter plot of example FIGS. 6A to 6G, theparameters directly extracted in accordance with embodiments can beconformed to the measured parameters.

In accordance with embodiments, the modeling can be made reflecting theparameters of the varactor varied according to frequency so that a moreaccurate RF modeling of a passive device can be made. Also, an accuratemodeling of the varactor can be made through the direct extractionmethod of the parameters so that the parameters of the varactor having aphysical meaning can be extracted without using an expensive CAD tooland the time required for optimizing the parameters can be reduced.Finally, since embodiments can include the direct extraction method ofthe parameters, a computing time can be shortened, an initial conditiondependency generated in performing the optimization is not required, anda pattern for a test is not required.

Although embodiments have been described herein, it should be understoodthat numerous other modifications and embodiments can be devised bythose skilled in the art that will fall within the spirit and scope ofthe principles of this disclosure. More particularly, various variationsand modifications are possible in the component parts and/orarrangements of the subject combination arrangement within the scope ofthe disclosure, the drawings and the appended claims. In addition tovariations and modifications in the component parts and/or arrangements,alternative uses will also be apparent to those skilled in the art.

1. A method comprising: using a processor to perform steps of: providingMOS varactor including a gate, a source, and a drain formed over ap-type semiconductor substrate, calculating a first port gate impedanceZ_(A), a second port bulk impedance Z_(B) and a substrate impedanceZ_(C) in a measured s-parameter using a first model equationRe(Z _(A))=Re(Z ₁₁ −Z ₁₂)=R _(gate) and a second model equation${{{Im}\left( Z_{A} \right)} = {{{Im}\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}},$where L_(gate) represents the overall inductance of the first port viaand the gate, R_(gate) represents a unit cell via/contact resistance ofthe first port and the gate, and C_(var) is formed of Cgate and C_(par),where C_(gate) represents a variable capacity of a MOS-type variablecapacitance and C_(par) represents a parasitic capacitance of thevaractor, parameters Z₁₁ and Z₁₂ are values obtained by transforming themeasured s-parameter, and ω is a constant.
 2. The method of claim 1,wherein Cvar is directly extracted from equations: $\begin{matrix}{{\frac{1}{{Im}\left( Z_{A} \right)} = {\frac{1}{{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}} = {\frac{{- \omega}\; C_{var}}{1 - {\omega^{2}L_{gate}C_{var}}} \approx {{- \omega}\; C_{var}}}}},} \\{{{{Im}\left( Z_{A} \right)} = {{{Im}\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}},\;{and}} \\{{{{Im}\left( Z_{A} \right)} + \frac{1}{\omega\; C_{var}}} = {\omega\;{L.}}}\end{matrix}$
 3. The method of claim 2, wherein the parameters Rsub andCsub are extracted from equations: $\begin{matrix}{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = {\frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}\mspace{14mu}{and}}}} \\{{\frac{- 1}{{Im}\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}},}\end{matrix}$ where C_(j) is a junction capacitance between a n-typeregion in the semiconductor substrate area and the p-type semiconductorsubstrate.
 4. The method of claim 1, wherein parameters Rsd, Lsd, andLgate are directly extracted from equations:Re(Z _(B))=Re(Z ₂₂ −Z ₁₂)=R _(sd) and Im(Z _(B))Im(Z ₂₂ −Z ₁₂)=jωL_(sd), where R_(sd) represents a unit cell via/contact resistance of thesecond port and a bulk terminal, L_(sd) represents an overall inductanceof the second port via and the bulk terminal, L_(gate) represents anoverall inductance of the first port via and the gate and Z₂₁ and Z₂₂are values obtained by transforming the measured s-parameter.
 5. Themethod of claim 2, wherein parameters Rsd, Lsd, and Lgate are directlyextracted from equations:Re(Z _(B))Re(Z ₂₂ −Z ₁₂)=R _(sd) and Im(Z _(B))=Im(Z ₂₂ −Z ₁₂)=jωL_(sd).
 6. The method of claim 5, wherein parameters Rsub and Csub aredirectly extracted from equations: $\begin{matrix}{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = {\frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}\mspace{14mu}{and}}}} \\{{\frac{- 1}{{Im}\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}},}\end{matrix}$ where C_(j) is a junction capacitance between a n+-typeregion in the semiconductor substrate area and the p-type semiconductorsubstrate.
 7. The method of claim 4, wherein the parameters Rsub andCsub are directly extracted from equations: $\begin{matrix}{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = {\frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}\mspace{14mu}{and}}}} \\{{\frac{- 1}{{Im}\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}},}\end{matrix}$ where C_(j) is a junction capacitance between a n+-typeregion in the semiconductor substrate area and the p-type semiconductorsubstrate.
 8. The method of claim 1, wherein the parameters Rsub andCsub are extracted from equations: $\begin{matrix}{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = {\frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}\mspace{14mu}{and}}}} \\{{\frac{- 1}{{Im}\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}},}\end{matrix}$ where C_(j) is a junction capacitance between a n+-typeregion in the semiconductor substrate area and the p-type semiconductorsubstrate.
 9. The method of claim 1, wherein Rgate comprises aresistance component by way of a polysilicon regardless of a gate bias.10. The method of claim 1, wherein L_(gate) has an inductance valuethrough a gate connection.
 11. The method of claim 1, wherein C_(gate)comprises a capacitor made by way of a depletion layer, whereby itsvalue can be very small in a depletion state.
 12. The method of claim 1,wherein R_(sd) comprises a channel resistance from the source to thedepletion layer.
 13. The method of claim 1, wherein Z_(A) and Z_(B) arehigh in frequency dependence.
 14. A method, using a processor, formodeling a MOS varactor including a gate, a source, and a drain formedover a p-type semiconductor substrate, the varactor having parametersincluding a first port gate impedance Z_(A) and a second port bulkimpedance Z_(B), a substrate impedance Z_(C), a parameter R_(gate)representing a unit cell via/contact resistance of the first port andthe gate that are directly extracted from the following model equations;${{{Re}\;\left( Z_{A} \right)} = {{{Re}\;\left( {Z_{11} - Z_{12}} \right)} = R_{gate}}},{{{Im}\;\left( Z_{A} \right)} = {{{Im}\;\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}},{{{Re}\;\left( Z_{B} \right)} = {{{Re}\;\left( {Z_{22} - Z_{12}} \right)} = R_{sd}}},{{{Im}\;\left( Z_{B} \right)} = {{{Im}\;\left( {Z_{22} - Z_{12}} \right)} = {j\;\omega\; L_{sd}}}},{{{Re}\;\left( Z_{C} \right)} = {{{Re}\;\left( Z_{12} \right)} = \frac{R_{sub}}{1 + {\omega^{2}\; R_{sub}^{2}\; C_{sub}^{2}}}}},{and}$${\frac{- 1}{{Im}\;\left( Z_{C} \right)} = \frac{{\omega\; C_{j}} + {\omega^{3}\; R_{sub}^{2}\; C_{sub}^{2}\; C_{j}}}{1 + {\omega^{2}\; R_{sub}^{2}\; C_{sub}\;\left( {C_{sub} + C_{j}} \right)}}},$where L_(gate) represents the overall inductance of the first port viaand the gate, R_(gate) represents the unit cell via/contact resistanceof the first port and the gate, C_(par) represents a parasiticcapacitance of the varactor, C_(gate) represents a variable capacity ofvariable capacitance, R_(sd) represents a unit cell via/contactresistance of the second port and a bulk terminal, L_(sd) represents anoverall inductance of the second port via and the bulk terminal, R_(sub)represents a resistance of the p-type semiconductor substrate, andC_(sub) represents a capacitance of the p-type semiconductor substrate.15. The method of claim 14, wherein the parameter C_(var) is directlyextracted from the following model equations: $\begin{matrix}{{\frac{1}{{Im}\left( Z_{A} \right)} = {\frac{1}{{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}} = {\frac{{- \omega}\; C_{var}}{1 - {\omega^{2}L_{gate}C_{var}}} \approx {{- \omega}\; C_{var}}}}},} \\{{{{Im}\left( Z_{A} \right)} = {{{Im}\left( {Z_{11} - Z_{12}} \right)} = {{\omega\; L_{gate}} - \frac{1}{\omega\; C_{var}}}}},{and}} \\{{{{Im}\left( Z_{A} \right)} + \frac{1}{\omega\; C_{var}}} = {\omega\;{L.}}}\end{matrix}$
 16. The method of claim 15, wherein the parameters R_(sd),L_(sd), and L_(gate) are directly extracted from the following modelequations:Re(Z _(B))=Re(Z ₂₂ −Z ₁₂)=R _(sd), andIm(Z _(B))=Im(Z ₂₂ −Z ₁₂)=jωL _(sd).
 17. The method of claim 15, whereinthe parameters R_(sub) and C_(sub) are extracted from the followingmodel equations: $\begin{matrix}{{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = \frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}}},{and}} \\{\frac{- 1}{{Im}\left( Z_{C} \right)} = {\frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}.}}\end{matrix}$
 18. The method of claim 14, wherein the parameters R_(sub)and C_(sub) are directly extracted from the following model equations:$\begin{matrix}{{{{Re}\left( Z_{C} \right)} = {{{Re}\left( Z_{12} \right)} = \frac{R_{sub}}{1 + {\omega^{2}R_{sub}^{2}C_{sub}^{2}}}}},{and}} \\{\frac{- 1}{{Im}\left( Z_{C} \right)} = {\frac{{\omega\; C_{j}} + {\omega^{3}R_{sub}^{2}C_{sub}^{2}C_{j}}}{1 + {\omega^{2}R_{sub}^{2}{C_{sub}\left( {C_{sub} + C_{j}} \right)}}}.}}\end{matrix}$